Lattice Synthesis Timing Report
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Lattice Synthesis Timing Report, Version
Mon Dec 18 08:38:54 2017
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Design: i2c_master
Constraint file:
Report level: verbose report, limited to 3 items per constraint
--------------------------------------------------------------------------------
================================================================================
Constraint: create_clock -period 1000.000000 -name clk2 [get_nets \i2c_master_config_inst/i2c_ack[2]]
39 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 995.281ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3AX CK \i2c_master_config_inst/wave_rom_address_1108__i0 (from \i2c_master_config_inst/i2c_ack[2] +)
Destination: FD1S3AX D \i2c_master_config_inst/wave_rom_address_1108__i7 (to \i2c_master_config_inst/i2c_ack[2] +)
Delay: 4.559ns (51.3% logic, 48.7% route), 6 logic levels.
Constraint Details:
4.559ns data_path \i2c_master_config_inst/wave_rom_address_1108__i0 to \i2c_master_config_inst/wave_rom_address_1108__i7 meets
1000.000ns delay constraint less
0.160ns L_S requirement (totaling 999.840ns) by 995.281ns
Path Details: \i2c_master_config_inst/wave_rom_address_1108__i0 to \i2c_master_config_inst/wave_rom_address_1108__i7
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q \i2c_master_config_inst/wave_rom_address_1108__i0 (from \i2c_master_config_inst/i2c_ack[2])
Route 2 e 1.198 wave_rom_address[0]
A1_TO_FCO --- 0.827 A[2] to COUT \i2c_master_config_inst/wave_rom_address_1108_add_4_1
Route 1 e 0.020 \i2c_master_config_inst/n6017
FCI_TO_FCO --- 0.157 CIN to COUT \i2c_master_config_inst/wave_rom_address_1108_add_4_3
Route 1 e 0.020 \i2c_master_config_inst/n6018
FCI_TO_FCO --- 0.157 CIN to COUT \i2c_master_config_inst/wave_rom_address_1108_add_4_5
Route 1 e 0.020 \i2c_master_config_inst/n6019
FCI_TO_FCO --- 0.157 CIN to COUT \i2c_master_config_inst/wave_rom_address_1108_add_4_7
Route 1 e 0.020 \i2c_master_config_inst/n6020
FCI_TO_F --- 0.598 CIN to S[2] \i2c_master_config_inst/wave_rom_address_1108_add_4_9
Route 1 e 0.941 \i2c_master_config_inst/n38
--------
4.559 (51.3% logic, 48.7% route), 6 logic levels.
Passed: The following path meets requirements by 995.458ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3AX CK \i2c_master_config_inst/wave_rom_address_1108__i2 (from \i2c_master_config_inst/i2c_ack[2] +)
Destination: FD1S3AX D \i2c_master_config_inst/wave_rom_address_1108__i7 (to \i2c_master_config_inst/i2c_ack[2] +)
Delay: 4.382ns (49.8% logic, 50.2% route), 5 logic levels.
Constraint Details:
4.382ns data_path \i2c_master_config_inst/wave_rom_address_1108__i2 to \i2c_master_config_inst/wave_rom_address_1108__i7 meets
1000.000ns delay constraint less
0.160ns L_S requirement (totaling 999.840ns) by 995.458ns
Path Details: \i2c_master_config_inst/wave_rom_address_1108__i2 to \i2c_master_config_inst/wave_rom_address_1108__i7
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q \i2c_master_config_inst/wave_rom_address_1108__i2 (from \i2c_master_config_inst/i2c_ack[2])
Route 2 e 1.198 wave_rom_address[2]
A1_TO_FCO --- 0.827 A[2] to COUT \i2c_master_config_inst/wave_rom_address_1108_add_4_3
Route 1 e 0.020 \i2c_master_config_inst/n6018
FCI_TO_FCO --- 0.157 CIN to COUT \i2c_master_config_inst/wave_rom_address_1108_add_4_5
Route 1 e 0.020 \i2c_master_config_inst/n6019
FCI_TO_FCO --- 0.157 CIN to COUT \i2c_master_config_inst/wave_rom_address_1108_add_4_7
Route 1 e 0.020 \i2c_master_config_inst/n6020
FCI_TO_F --- 0.598 CIN to S[2] \i2c_master_config_inst/wave_rom_address_1108_add_4_9
Route 1 e 0.941 \i2c_master_config_inst/n38
--------
4.382 (49.8% logic, 50.2% route), 5 logic levels.
Passed: The following path meets requirements by 995.458ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3AX CK \i2c_master_config_inst/wave_rom_address_1108__i1 (from \i2c_master_config_inst/i2c_ack[2] +)
Destination: FD1S3AX D \i2c_master_config_inst/wave_rom_address_1108__i7 (to \i2c_master_config_inst/i2c_ack[2] +)
Delay: 4.382ns (49.8% logic, 50.2% route), 5 logic levels.
Constraint Details:
4.382ns data_path \i2c_master_config_inst/wave_rom_address_1108__i1 to \i2c_master_config_inst/wave_rom_address_1108__i7 meets
1000.000ns delay constraint less
0.160ns L_S requirement (totaling 999.840ns) by 995.458ns
Path Details: \i2c_master_config_inst/wave_rom_address_1108__i1 to \i2c_master_config_inst/wave_rom_address_1108__i7
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q \i2c_master_config_inst/wave_rom_address_1108__i1 (from \i2c_master_config_inst/i2c_ack[2])
Route 2 e 1.198 wave_rom_address[1]
A1_TO_FCO --- 0.827 A[2] to COUT \i2c_master_config_inst/wave_rom_address_1108_add_4_3
Route 1 e 0.020 \i2c_master_config_inst/n6018
FCI_TO_FCO --- 0.157 CIN to COUT \i2c_master_config_inst/wave_rom_address_1108_add_4_5
Route 1 e 0.020 \i2c_master_config_inst/n6019
FCI_TO_FCO --- 0.157 CIN to COUT \i2c_master_config_inst/wave_rom_address_1108_add_4_7
Route 1 e 0.020 \i2c_master_config_inst/n6020
FCI_TO_F --- 0.598 CIN to S[2] \i2c_master_config_inst/wave_rom_address_1108_add_4_9
Route 1 e 0.941 \i2c_master_config_inst/n38
--------
4.382 (49.8% logic, 50.2% route), 5 logic levels.
Report: 4.719 ns is the maximum delay for this constraint.
================================================================================
Constraint: create_clock -period 1000.000000 -name clk1 [get_nets clk_div_100k]
1896 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 987.963ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3IX CK \i2c_master_config_inst/i2c_master_logic_inst/state_current__i7 (from clk_div_100k +)
Destination: FD1P3AY D \i2c_master_config_inst/i2c_master_logic_inst/sda_r_512 (to clk_div_100k +)
Delay: 11.877ns (28.6% logic, 71.4% route), 7 logic levels.
Constraint Details:
11.877ns data_path \i2c_master_config_inst/i2c_master_logic_inst/state_current__i7 to \i2c_master_config_inst/i2c_master_logic_inst/sda_r_512 meets
1000.000ns delay constraint less
0.160ns L_S requirement (totaling 999.840ns) by 987.963ns
Path Details: \i2c_master_config_inst/i2c_master_logic_inst/state_current__i7 to \i2c_master_config_inst/i2c_master_logic_inst/sda_r_512
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q \i2c_master_config_inst/i2c_master_logic_inst/state_current__i7 (from clk_div_100k)
Route 18 e 1.879 \i2c_master_config_inst/i2c_master_logic_inst/state_current[6]
LUT4 --- 0.493 A to Z \i2c_master_config_inst/i2c_master_logic_inst/equal_1402_i24_2_lut_rep_67
Route 9 e 1.574 \i2c_master_config_inst/i2c_master_logic_inst/n6650
LUT4 --- 0.493 C to Z \i2c_master_config_inst/i2c_master_logic_inst/i1_2_lut_rep_46_3_lut_4_lut
Route 1 e 0.941 \i2c_master_config_inst/i2c_master_logic_inst/n6629
LUT4 --- 0.493 D to Z \i2c_master_config_inst/i2c_master_logic_inst/i3_4_lut_adj_49
Route 3 e 1.258 \i2c_master_config_inst/i2c_master_logic_inst/n25_adj_653
LUT4 --- 0.493 B to Z \i2c_master_config_inst/i2c_master_logic_inst/select_638_Select_0_i15_4_lut
Route 1 e 0.941 \i2c_master_config_inst/i2c_master_logic_inst/n15
LUT4 --- 0.493 A to Z \i2c_master_config_inst/i2c_master_logic_inst/i3_4_lut_adj_60
Route 1 e 0.941 \i2c_master_config_inst/i2c_master_logic_inst/n8
LUT4 --- 0.493 C to Z \i2c_master_config_inst/i2c_master_logic_inst/i1_4_lut_adj_59
Route 1 e 0.941 \i2c_master_config_inst/i2c_master_logic_inst/n6222
--------
11.877 (28.6% logic, 71.4% route), 7 logic levels.
Passed: The following path meets requirements by 987.963ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3IX CK \i2c_master_config_inst/i2c_master_logic_inst/state_current__i7 (from clk_div_100k +)
Destination: FD1P3AY D \i2c_master_config_inst/i2c_master_logic_inst/sda_ctl_511 (to clk_div_100k +)
Delay: 11.877ns (28.6% logic, 71.4% route), 7 logic levels.
Constraint Details:
11.877ns data_path \i2c_master_config_inst/i2c_master_logic_inst/state_current__i7 to \i2c_master_config_inst/i2c_master_logic_inst/sda_ctl_511 meets
1000.000ns delay constraint less
0.160ns L_S requirement (totaling 999.840ns) by 987.963ns
Path Details: \i2c_master_config_inst/i2c_master_logic_inst/state_current__i7 to \i2c_master_config_inst/i2c_master_logic_inst/sda_ctl_511
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q \i2c_master_config_inst/i2c_master_logic_inst/state_current__i7 (from clk_div_100k)
Route 18 e 1.879 \i2c_master_config_inst/i2c_master_logic_inst/state_current[6]
LUT4 --- 0.493 A to Z \i2c_master_config_inst/i2c_master_logic_inst/equal_1402_i24_2_lut_rep_67
Route 9 e 1.574 \i2c_master_config_inst/i2c_master_logic_inst/n6650
LUT4 --- 0.493 C to Z \i2c_master_config_inst/i2c_master_logic_inst/i1_2_lut_rep_46_3_lut_4_lut
Route 1 e 0.941 \i2c_master_config_inst/i2c_master_logic_inst/n6629
LUT4 --- 0.493 D to Z \i2c_master_config_inst/i2c_master_logic_inst/i3_4_lut_adj_49
Route 3 e 1.258 \i2c_master_config_inst/i2c_master_logic_inst/n25_adj_653
LUT4 --- 0.493 B to Z \i2c_master_config_inst/i2c_master_logic_inst/select_592_Select_0_i15_3_lut
Route 1 e 0.941 \i2c_master_config_inst/i2c_master_logic_inst/n15_adj_672
LUT4 --- 0.493 C to Z \i2c_master_config_inst/i2c_master_logic_inst/i5_4_lut
Route 1 e 0.941 \i2c_master_config_inst/i2c_master_logic_inst/n12
LUT4 --- 0.493 C to Z \i2c_master_config_inst/i2c_master_logic_inst/i1_4_lut_adj_78
Route 1 e 0.941 \i2c_master_config_inst/i2c_master_logic_inst/n6226
--------
11.877 (28.6% logic, 71.4% route), 7 logic levels.
Passed: The following path meets requirements by 987.966ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3IX CK \i2c_master_config_inst/i2c_master_logic_inst/state_current__i13 (from clk_div_100k +)
Destination: FD1P3AY D \i2c_master_config_inst/i2c_master_logic_inst/sda_r_512 (to clk_div_100k +)
Delay: 11.874ns (28.7% logic, 71.3% route), 7 logic levels.
Constraint Details:
11.874ns data_path \i2c_master_config_inst/i2c_master_logic_inst/state_current__i13 to \i2c_master_config_inst/i2c_master_logic_inst/sda_r_512 meets
1000.000ns delay constraint less
0.160ns L_S requirement (totaling 999.840ns) by 987.966ns
Path Details: \i2c_master_config_inst/i2c_master_logic_inst/state_current__i13 to \i2c_master_config_inst/i2c_master_logic_inst/sda_r_512
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q \i2c_master_config_inst/i2c_master_logic_inst/state_current__i13 (from clk_div_100k)
Route 17 e 1.876 \i2c_master_config_inst/i2c_master_logic_inst/state_current[13]
LUT4 --- 0.493 B to Z \i2c_master_config_inst/i2c_master_logic_inst/equal_1402_i24_2_lut_rep_67
Route 9 e 1.574 \i2c_master_config_inst/i2c_master_logic_inst/n6650
LUT4 --- 0.493 C to Z \i2c_master_config_inst/i2c_master_logic_inst/i1_2_lut_rep_46_3_lut_4_lut
Route 1 e 0.941 \i2c_master_config_inst/i2c_master_logic_inst/n6629
LUT4 --- 0.493 D to Z \i2c_master_config_inst/i2c_master_logic_inst/i3_4_lut_adj_49
Route 3 e 1.258 \i2c_master_config_inst/i2c_master_logic_inst/n25_adj_653
LUT4 --- 0.493 B to Z \i2c_master_config_inst/i2c_master_logic_inst/select_638_Select_0_i15_4_lut
Route 1 e 0.941 \i2c_master_config_inst/i2c_master_logic_inst/n15
LUT4 --- 0.493 A to Z \i2c_master_config_inst/i2c_master_logic_inst/i3_4_lut_adj_60
Route 1 e 0.941 \i2c_master_config_inst/i2c_master_logic_inst/n8
LUT4 --- 0.493 C to Z \i2c_master_config_inst/i2c_master_logic_inst/i1_4_lut_adj_59
Route 1 e 0.941 \i2c_master_config_inst/i2c_master_logic_inst/n6222
--------
11.874 (28.7% logic, 71.3% route), 7 logic levels.
Report: 12.037 ns is the maximum delay for this constraint.
================================================================================
Constraint: create_clock -period 1000.000000 -name clk0 [get_nets sys_clk_12m_c]
1605 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 989.813ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3IX CK \clk_div_inst/cnt_p_1107__i26 (from sys_clk_12m_c +)
Destination: FD1S3IX CD \clk_div_inst/cnt_p_1107__i30 (to sys_clk_12m_c +)
Delay: 10.027ns (29.0% logic, 71.0% route), 6 logic levels.
Constraint Details:
10.027ns data_path \clk_div_inst/cnt_p_1107__i26 to \clk_div_inst/cnt_p_1107__i30 meets
1000.000ns delay constraint less
0.160ns L_S requirement (totaling 999.840ns) by 989.813ns
Path Details: \clk_div_inst/cnt_p_1107__i26 to \clk_div_inst/cnt_p_1107__i30
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q \clk_div_inst/cnt_p_1107__i26 (from sys_clk_12m_c)
Route 3 e 1.315 \clk_div_inst/cnt_p[26]
LUT4 --- 0.493 B to Z \clk_div_inst/i8_2_lut
Route 1 e 0.941 \clk_div_inst/n34
LUT4 --- 0.493 C to Z \clk_div_inst/i22_4_lut
Route 1 e 0.941 \clk_div_inst/n48
LUT4 --- 0.493 B to Z \clk_div_inst/i24_4_lut
Route 1 e 0.941 \clk_div_inst/n50
LUT4 --- 0.493 B to Z \clk_div_inst/i25_4_lut
Route 1 e 0.941 \clk_div_inst/n6086
LUT4 --- 0.493 A to Z \clk_div_inst/i4188_4_lut
Route 32 e 2.039 \clk_div_inst/n4410
--------
10.027 (29.0% logic, 71.0% route), 6 logic levels.
Passed: The following path meets requirements by 989.813ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3IX CK \clk_div_inst/cnt_p_1107__i26 (from sys_clk_12m_c +)
Destination: FD1S3IX CD \clk_div_inst/cnt_p_1107__i29 (to sys_clk_12m_c +)
Delay: 10.027ns (29.0% logic, 71.0% route), 6 logic levels.
Constraint Details:
10.027ns data_path \clk_div_inst/cnt_p_1107__i26 to \clk_div_inst/cnt_p_1107__i29 meets
1000.000ns delay constraint less
0.160ns L_S requirement (totaling 999.840ns) by 989.813ns
Path Details: \clk_div_inst/cnt_p_1107__i26 to \clk_div_inst/cnt_p_1107__i29
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q \clk_div_inst/cnt_p_1107__i26 (from sys_clk_12m_c)
Route 3 e 1.315 \clk_div_inst/cnt_p[26]
LUT4 --- 0.493 B to Z \clk_div_inst/i8_2_lut
Route 1 e 0.941 \clk_div_inst/n34
LUT4 --- 0.493 C to Z \clk_div_inst/i22_4_lut
Route 1 e 0.941 \clk_div_inst/n48
LUT4 --- 0.493 B to Z \clk_div_inst/i24_4_lut
Route 1 e 0.941 \clk_div_inst/n50
LUT4 --- 0.493 B to Z \clk_div_inst/i25_4_lut
Route 1 e 0.941 \clk_div_inst/n6086
LUT4 --- 0.493 A to Z \clk_div_inst/i4188_4_lut
Route 32 e 2.039 \clk_div_inst/n4410
--------
10.027 (29.0% logic, 71.0% route), 6 logic levels.
Passed: The following path meets requirements by 989.813ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3IX CK \clk_div_inst/cnt_p_1107__i26 (from sys_clk_12m_c +)
Destination: FD1S3IX CD \clk_div_inst/cnt_p_1107__i28 (to sys_clk_12m_c +)
Delay: 10.027ns (29.0% logic, 71.0% route), 6 logic levels.
Constraint Details:
10.027ns data_path \clk_div_inst/cnt_p_1107__i26 to \clk_div_inst/cnt_p_1107__i28 meets
1000.000ns delay constraint less
0.160ns L_S requirement (totaling 999.840ns) by 989.813ns
Path Details: \clk_div_inst/cnt_p_1107__i26 to \clk_div_inst/cnt_p_1107__i28
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q \clk_div_inst/cnt_p_1107__i26 (from sys_clk_12m_c)
Route 3 e 1.315 \clk_div_inst/cnt_p[26]
LUT4 --- 0.493 B to Z \clk_div_inst/i8_2_lut
Route 1 e 0.941 \clk_div_inst/n34
LUT4 --- 0.493 C to Z \clk_div_inst/i22_4_lut
Route 1 e 0.941 \clk_div_inst/n48
LUT4 --- 0.493 B to Z \clk_div_inst/i24_4_lut
Route 1 e 0.941 \clk_div_inst/n50
LUT4 --- 0.493 B to Z \clk_div_inst/i25_4_lut
Route 1 e 0.941 \clk_div_inst/n6086
LUT4 --- 0.493 A to Z \clk_div_inst/i4188_4_lut
Route 32 e 2.039 \clk_div_inst/n4410
--------
10.027 (29.0% logic, 71.0% route), 6 logic levels.
Report: 10.187 ns is the maximum delay for this constraint.
Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint | Constraint| Actual|Levels
--------------------------------------------------------------------------------
| | |
create_clock -period 1000.000000 -name | | |
clk2 [get_nets | | |
\i2c_master_config_inst/i2c_ack[2]] | 1000.000 ns| 4.719 ns| 6
| | |
create_clock -period 1000.000000 -name | | |
clk1 [get_nets clk_div_100k] | 1000.000 ns| 12.037 ns| 7
| | |
create_clock -period 1000.000000 -name | | |
clk0 [get_nets sys_clk_12m_c] | 1000.000 ns| 10.187 ns| 6
| | |
--------------------------------------------------------------------------------
All constraints were met.
Timing summary:
---------------
Timing errors: 0 Score: 0
Constraints cover 3540 paths, 354 nets, and 981 connections (96.6% coverage)
Peak memory: 69513216 bytes, TRCE: 0 bytes, DLYMAN: 0 bytes
CPU_TIME_REPORT: 0 secs